This invention relates to a technique applicable to the technology of semiconductor integrated circuits and semiconductor storage devices, and more particularly relates to a technique for a semiconductor storage device which is provided, for instance, with spare memory columns or memory rows and a redundancy circuit.
In a semiconductor storage device such as RAM (Random Access Memory), the reduction of yield due to a defective bit or the occurrence of a defective word line such as a disconnection or short circuit thereof becomes more likely as the capacity of the memory array increases. In order to improve this yield, it has been proposed to provide a redundancy circuit which can cope successfully with the defective bit and the defective word line by substituting a spare memory column or memory row prepared separately for the defective word line in a memory array.
The present inventors have developed, as one system of such a redundancy circuit construction, a system in which a means for setting an address of a memory column or a memory row containing the defective bit (hereinafter called defective address) and an address comparator circuit comparing the defective address set in said means with an input address are provided. A spare memory column or memory row is selected in place of the regular memory column or memory row when the aforesaid two addresses coincide with each other.
FIG. 1 shows a schematic construction of this system.
In the figure, numeral 1 denotes an address buffer which forms internal address signals axi and axi based on an address signal Axi input from external equipment to an address decoder which decodes internal address signals axi and axi supplied from the address buffer 1. Numeral 3 denotes an address comparator circuit having a defective address setting means therein. This circuit compares the internal address signals axi and axi supplied from the address buffer 1 with a defective address set beforehand in the defective address setting means, and delivers a coincide signal .phi.sj when said address signals and the defective address coincide completely with one another. A selection signal forming circuit 4 delivers a redundancy selection signal .phi.xsj for selecting a spare memory row, when said coincidence signal .phi.sj is supplied thereto. At that time, a selection signal .phi.xij is not output. A word line driver 5s, which is made to correspond to the spare memory row to be substituted for the memory row of the defective address, is driven by the redundancy selection signal .phi.xsj. As the result, a word line of the spare memory row is selected.
When the coincidence of the addresses is not detected, the signal .phi.xsj is not output. In this case, the selection signal .phi.xij is output from a selection signal forming circuit 4. At this time, a word line driver 5 selected by the decoder 2 is driven. As the result, a regular word line is selected.
In the redundancy circuit of such an address comparison system as described above, an operation of comparing addresses is executed axi' internal address signals axi, axi supplied from the address buffer 1 not only when a spare memory row is selected, but also when a regular memory row is selected. This causes a problem in that access time is delayed by a time period required for the comparison of addresses.